For complementary metal oxide semiconductor (CMOS) and similar transistor architectures, a transistor can be modeled as a five terminal component whereby the current flow through the transistor is controlled by the relative voltage potentials at its five terminals: source, gate, drain, body or well, and substrate. In normal operating conditions, in order to prevent currents from flowing in, for example, a p-type transistor, the gate terminal is biased at a voltage Vg higher than both the source voltage Vs and the drain voltage Vd and less than a threshold voltage Vtp (e.g., Vg>max(Vs, Vd)+Vtp). At the same time the intrinsic junction diodes at the source to body junction, the drain to body junction, and the substrate to body junction are kept reverse biased. However, the magnitudes of the voltages applicable to the electrodes of a transistor may vary with respect to each other in a non-determinate or non-ordered manner, such as during the power-down or power-up sequence of the device in which the transistor is implemented. In such circumstances, it can be undesirable to fixedly connect the well of a transistor to a particular electrode of the transistor so that the well and the electrode are always biased by the same voltage because that voltage may not be the highest voltage applied to the electrodes of the transistor when attempting to render the transistor non-conductive. If the gate is not biased to the highest voltage at the source—drain electrodes of the transistor (for a p-type transistor), the transistor typically may remain conductive through the channel. If the well is not biased at a voltage higher than the voltage potentials at the source, drain and substrate, reverse currents may be injected possibly leading to undesired circuit behavior, including latch-up.
To prevent the possibility of reverse currents and relative effects, biasing circuits have been developed to allow one of two voltages to be used as a well biasing voltage. However, these circuits typically are not scalable to accommodate selection between more than two voltages. Further, the selection between the two available voltages typically is enacted in response to control signals that are generated based on “a priori” knowledge of which voltage will be the highest (or, alternately, lowest) of the two voltages at any given time. As such, their reliance on a determinate relationship between the two selectable voltages are of limited or no use in contexts whereby the voltages may be fluctuating unpredictably with respect to each other or whereby the highest (or lowest) of three or more voltages is to be used in biasing the wells of transistors so as to render them non-conductive. Accordingly, an improved technique for biasing a well of a transistor would be advantageous.